The following disclosure relates to electrical circuits and signal processing.
Analog-to-digital conversion is the process of converting an analog input signal, that is typically represented as voltage, into a digital format. Flash (or parallel) and pipelined are examples of conventional analog-to-digital conversion architectures.
A conventional flash analog-to-digital conversion architecture generally provides a fast quantization rate per analog input signal sample. Quantization is a process for determining a digital value which represents a particular analog signal. In the flash analog-to-digital conversion architecture, a digital value can be generated per clock cycle for each analog input signal sample, without regard to N, where N represents the number of bits of resolution. A conventional flash analog-to-digital conversion architecture, however, requires that all quantization levels be simultaneously compared to a given analog input signal sample. Thus, a conventional flash analog-to-digital conversion architecture generally requires use of 2n-1 comparators to achieve a digital value, with N bits of resolution, per clock cycle.
A conventional pipelined analog-to-digital conversion architecture includes a method of quantizing an analog input signal sample in stages. Generally, N sample-and-hold amplifier stages are required in a pipelined analog-to-digital conversion architecture, where N represents the number of bits of resolution.
Conventional flash analog-to-digital conversion architectures and conventional pipelined analog-to-digital conversion architectures generally consume a large amount of power due to the number of required comparators and the use of high-powered sample-and-hold amplifier stages, respectively. In addition, conventional flash analog-to-digital conversion architectures and conventional pipelined analog-to-digital conversion architectures typically require a clocking circuit which consumes additional power. For example, one comparator typically consumes 10 μA of power, and a clocking circuit typically consumes 50 μA of power. Thus, a conventional 4-bit flash analog-to-digital conversion architecture generally consumes approximately 245 μA of power, where a large percentage of the power consumption is due to use of 15 comparators and an associated clocking circuit.
In general, in one aspect, this specification describes an analog-to-digital converter having N comparators. Each one of the N comparators receives a common analog input signal at a corresponding first input, and each one of the N comparators provides an output representing one bit of an N-bit digital conversion of the common analog input signal. A pth one of the N comparators receives a pth reference voltage as a second input, wherein p=1, and each of i′ ones of the N comparators receives an i,th reference voltage at a respective second input in accordance with at least one respective output of j ones of the N comparators, in which p<i′≦N, p≦j<i′ and i′ and j are each integers.
Particular implementations can include one or more of the following features. The analog-to-digital converter can further include a reference voltage source that provides k voltages within a first pre-determined voltage range. An rth one of the k voltages is substantially ½ the first pre-determined voltage range and an rth voltage is input to the second input of the pth comparator, in which k=2N and r=k/2, and where r and k are integers. An mth voltage of the k voltages can be substantially equal to the first pre-determined voltage range divided by k and then multiplied by m, in which 1≦m≦k and m is an integer. The analog-to-digital converter can further include N selectors, in which an nth one of the N selectors selects ones of the k voltages as the second input of the nth comparator in accordance with the following equation: Vref(n,i)=V(2(N−n)+((i−1)*2(N−n)+1)), in which n represents an nth stage of the analog-to-digital converter, and i is an integer from 1 to n. Each of the i+1 selectors can include transistors implemented in a pass gate architecture. The pass gate architecture can include PMOS transistors. Each of the k voltages can be evenly spaced within a pre-determined voltage range.
In general, in another aspect, this specification describes an analog-to-digital converter including a reference generator and a comparator. The reference generator is operable to generate one or more reference voltages. The comparator is operable to receive an analog input signal and compare the analog input signal to one or more of the reference voltages using N comparators. The comparator is further operable to generate an N-bit digital signal representative of the analog input signal without using a reference clock, where N represents a bit resolution of the digital signal and N is an integer greater than 1.
Particular implementations can include one or more of the following features. The reference generator can generate 2N reference voltages. The analog-to-digital converter can further include a switch network operable to select ones of the one or more reference voltages and provide the selected reference voltages to the comparator for comparison with the analog input signal. The selected reference voltages can substantially represent a midpoint of a pre-determined voltage range. An output of each of the N comparators can form the N-bit digital signal representative of the analog input signal.
In general, in another aspect, this specification describes a method for determining a digital representation of a corresponding analog input signal. The method includes receiving an analog input signal; performing N comparisons of the analog input signal to one or more reference voltages; and using results of the N comparisons, forming an N-bit digital signal corresponding to the analog input signal. N represents a pre-determined bit resolution of a digital output signal and performing N comparisons includes performing N comparisons of the analog input signal to one or more reference voltages without using a reference clock.
Particular implementations can include one or more of the following features. The method can further include providing one or more reference voltages substantially representing a corresponding midpoint of a pre-determined voltage range. Performing N comparisons can include successively performing N comparisons using a binary search technique. Successively performing N comparisons can include determining N times if the analog input signal is greater than or less than N different reference voltages, in which each of the N different reference voltages substantially represent a corresponding midpoint of a corresponding pre-determined voltage range.
In general, in another aspect, this specification describes an apparatus including a circuit to generate an analog signal that varies slowly with respect to time; a reference generator operable to generate one or more reference voltages; and a comparator operable to receive the analog signal and compare the analog signal to one or more of the reference voltages using N comparators. The comparator is further operable to generate an N-bit digital signal representative of the analog signal without using a reference clock, in which N represents a bit resolution of the digital signal and N is an integer greater than 1.
Implementations can include one or more of the following advantages. An analog-to-digital conversion circuit is provided that includes a maximum of N comparators, where N represents the number of bits of resolution of a digital output signal. In addition, the analog-to-digital conversion circuit provided is asynchronous in that the analog-to-digital conversion circuit does not require a reference clock or a clocking circuit for converting an analog input signal into a digital format. Thus, for example, an analog-to-digital conversion circuit provided herein, using 4-bits of resolution, will generally consume a maximum of 85 μA of power, which is substantially less than conventional 4-bit flash analog-to-digital conversion architectures and conventional 4-bit pipelined analog-to-digital conversion architectures. Furthermore, in one implementation, the analog-to-digital conversion circuit includes a pass gate architecture that is used within an associated switch network. Use of a pass gate architecture eliminates the need of complex logic circuits, that may consume additional power.
The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features and advantages will be apparent from the description and drawings, and from the claims.
Like reference symbols in the various drawings indicate like elements.